1. Technical Field
The present invention relates to a semiconductor integrated circuit, and in particular, to a power-on reset circuit to be used in a semiconductor integrated circuit.
2. Related Art
In general, semiconductor integrated circuits generate power-on reset signals upon initial operation to initialize the operation of each of the internal circuits formed therein. In order to generate such power-on reset signals, the semiconductor integrated circuits have power-on reset circuits. General power-on reset circuits are configured as analog circuits so that, if a level of an external power supply voltage reaches a preset level upon the initial operation of semiconductor integrated circuits, power-on reset signals are enabled.
This analog-type power-on reset circuit includes a voltage detector configured to detect the level of the external power supply voltage, and a signal generator configured to generate a power-on reset signal on the basis of the level detection results by the voltage detector. The power-on reset circuit has a plurality of switching elements formed therein and each of the switching elements operates in response to continuous changes of a voltage level. The switching elements of the semiconductor integrated circuit may vary in their operation property according to a variation in PVT (process, voltage, and temperature). However, power-on reset circuits implemented as analog circuits are configured to have switching elements that are sensitive to variations in PVT. For this reason, stability in the operation is not ensured.
For example, if a variation in the property of the internal switching elements causes a phenomena such as glitches and the power-on reset signal is disabled in error at the time it should be enabled, each of the internal circuits of the semiconductor integrated circuit does not initialize, in which a normal operation of the semiconductor integrated circuit is not performed. As described above, since general power-on reset circuits are implemented as analog circuits, there are technical restrictions in the stability of the operation and the reliability of the general operation of the semiconductor integrated circuit is low.